In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage.

The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly ...

In this interview, Dr. Chady Stephan, PhD, the Applied Markets Leader at PerkinElmer, talks to AZoM about the current trends shaping semiconductor wafer manufacturing. A semiconductor is a material ...

Parallel piezo aligners with fly height sensors enable faster PIC wafer testing. SAN FRANCISCO, Jan. 21, 2026 /PRNewswire/ -- PI (Physik Instrumente) announced a new technology platform for ...

FormFactor has announced its new Takumi wafer-probe products, which use an interchangeable wafer-probe-card architecture for in-line process, reliability, and end-of-line parametric testing. The ...

FREMONT, CA / ACCESS Newswire / August 26, 2025 / Aehr Test Systems (AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has received a purchase order from a ...

This higher density of circuitry on a wafer requires greater accuracy and a highly fragile and advanced fabrication process. Several newer and highly complex ICs today are made of a dozen or more ...

CEA-Leti and Fraunhofer IPMS have successfully completed a first wafer exchange for a ferroelectric memory pilot line.